Kyumin Kwon’s research on automating analog circuit design earns Best Paper Award at SMACD23

Kwon combines a human knowledge-based model with an existing digital synthesis tool to significantly increase the speed of characterization and design for large scale analog circuits.
Kyumin Kwon
Kyumin Kwon

ECE PhD student Kyumin Kwon has been awarded a Best Paper Award at the 2023 International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuit Design (SMACD) in the category CAD/EDA Methodologies & Tools for AMS Systems.

Kwon presented an all-digital phase-locked loop (ADPLL) generator that can greatly improve the speed of characterization and design for clocking circuits. The automation methodology can help the integrated circuits industry operate efficiently under current time-to-market constraints, as well as help manage the complexity of the design process in sub 20nm technology.

Specifically, Kwon focused on synthesizable analog blocks, which have simple design parameters that are highly suitable for design automation. In addition, they can be easily combined with digital layout tools, which take advantage of existing layout design engines to manage complex design rules.

The paper, “Synthesizable ADPLL Generator: From Specification to GDS,” was co-authored by his advisor, Prof. David Wentzloff. The work was sponsored by the Defense Advanced Research Projects Agency (DARPA).