Edward S. Davidson
Edward S. Davidson was recruited to Michigan to be Chair of EECS in 1988. He was the first chair of the department with a specialty in computer science. After stepping down as Chair in 1990, he later served as Director of the Center for Parallel Computing (1994-97) and as Associate chair for the Division of Computer Science and Engineering (1997-2000).
Davidson received is B.A. in Mathematics from Harvard in 1961, his M.S. in Communication Science from Michigan in 1962, and his Ph.D. in Electrical Engineering from the University of Illinois in 1968. He was on the faculty at Stanford University and the University of Illinois before coming to Michigan.
At the University of Illinois, he had been the Associate Director of the Center for Supercomputing Research and Development, and managed the hardware design of the Cedar parallel supercomputer at the Center for Supercomputing Research and Development.
Davidson has done seminal work in computer architecture, supercomputing, parallel and pipeline processing, performance modeling, application code assessment and tuning, and intelligent caches. He pioneered pipelining techniques for improving processor throughput in both hardware and software. In the ‘70s, he developed the reservation table approach to optimum design and cyclic scheduling of pipelines, designed and implemented an eight-node symmetric multiprocessor (SMP) system in 1976, and developed a variety of systematic methods for modeling performance and enhancing systems, including early work on simulated annealing, wave pipelining, multiple instruction stream pipelines, decoupled access-execute architecture, and polycyclic scheduling (aka software pipelining).
Davidson earned the 1992 IEEE Harry H. Goode Memorial Award for “pivotal seminal contributions to the design, implementation, and performance evaluation of high performance computer systems,” the 1996 Taylor L. Booth Education Award for “contributions to the establishment of computer engineering as an academic discipline and for nurturing many leaders of this field during their formative years in the profession,” and the 2000 IEEE/ACM Eckert-Mauchly Award “for his seminal contributions to the design, implementation, and performance evaluation of high performance pipelines and multiprocessor systems.” He is a Fellow of the IEEE.