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Zhengya Zhang earns Best Paper Award at Symposium on VLSI Circuits

The resulting 65nm CMOS test chip achieved an energy efficiency of 21 pJ/bit making it a promising candidate for low-power, high-performance applications.

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Assistant professor Zhengya Zhang and collaborators Venkat Anantharam (Professor, UC Berkeley EECS), Martin J. Wainwright (Professor, UC Berkeley EECS), and Borivoje Nikolic (Professor, UC Berkeley EECS), were awarded the Best Paper Award at the 2010 Symposium on VLSI Circuits. The paper was presented at the 2009 Symposium.

The paper, entitled �A 47 Gb/s LDPC Decoder with Improved Low Error Rate Performance,� demonstrates a record LDPC decoding throughput for high-speed communication with enhanced coding gain down to the bit error rate of 10-14. The researchers achieved this performance by unique algorithm and architectural approaches: a post-processing algorithm was created to lower the error floor by several orders of magnitude and enable the use a short word length of 4 bits; a grouped parallel architecture optimizes the silicon area and power efficiencies by aggressively scaling down the on-chip interconnection overhead. The resulting 65nm CMOS test chip achieved an energy efficiency of 21 pJ/bit � making it a promising candidate for low-power, high-performance applications in data storage, high-speed wireless and optical communications.

Prof. Zhang�s research interest is in energy-efficient and error-resilient communication and signal processing systems. Recent focus areas include error-resilient processors, low-power communication processors, and accelerators for imaging applications.

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